The present invention relates to a method for manufacturing a semiconductor device. Specifically, the invention relates to a method for manufacturing a power super-junction semiconductor device (hereinafter referred to as an “SJ-MOSFET”).
MOSFET's that break the conventional characteristics limits have been proposed. The MOSFET's include an alternating conductivity type layer that constitutes a drift layer on the major surface of a heavily doped semiconductor substrate (or a semiconductor substrate exhibiting low electrical resistance). The alternating conductivity type layer is an aggregate having the so-called “super-junction structure” formed of columnar p-type regions and columnar n-type regions. The columnar p-type regions and columnar n-type regions are formed in perpendicular to the major surface of the semiconductor substrate. The columnar p-type regions and columnar n-type regions are arranged in close contact with each other and alternately in parallel to the major surface of the semiconductor substrate. Hereinafter, the super-junction structure as described above will be referred to sometimes as the “p- and n-type columnar structure” or the “SJ columnar structure”.
MOSFET's having the super-junction structure manufactured by the multi-step epitaxial growth method have been mass-produced already. The multi-step epitaxial growth method grows epitaxial layers, which constitute a drift layer on a semiconductor substrate exhibiting low resistance, layer by layer. In every stage of growing an epitaxial layer, patterning and ion implantation for forming p-type regions and patterning and ion implantation for forming n-type regions are conducted. And, the growth of an epitaxial layer and the patterning and ion implantation for forming p-type regions and n-type regions are repeated to laminate the epitaxial layers and to grow the p-type regions and n-type regions in perpendicular to the substrate major surface.
The multi-step epitaxial growth method preferably aggregates the p-type regions and n-type regions formed in perpendicular to the substrate major surface such that the p-type regions and n-type regions are in close contact with each other and arranged alternately along the substrate major surface. The multi-step epitaxial growth method preferably determines the dimensions and structures of the p-type regions and n-type regions suitable for making a current flow in the ON-state of the device and for being depleted in the OFF-state of the device. In short, the multi-step epitaxial growth method is preferable for forming the so-called super junction structure. However, the manufacturing process of the multi-step epitaxial growth method is long and complicated, increasing the manufacturing costs and the chip costs.
Recently, an epitaxial trench filling method, which facilitates manufacturing a super-junction structure similar to the super-junction structure described above and reducing the manufacturing costs, has been developed. The epitaxial trench filling method employs a wafer including a heavily doped n-type semiconductor substrate and an n-type epitaxial layer grown on the heavily doped n-type semiconductor substrate and having a predetermined thickness. The n-type epitaxial layer will work for a drift layer.
An oxide film or such a film that will work for an etching mask is formed on the wafer. Patterning is conducted to form openings in the oxide film at predetermined intervals for forming trenches. Using the remaining portion of the oxide film for a trench etching mask, trenches with a high aspect ratio are formed by reactive ion etching (hereinafter referred to as “RIE”) through the n-type epitaxial layer or closely to the boundary between the n-type epitaxial layer and the n-type semiconductor substrate.
Then, a p-type epitaxial layer is grown in the trenches to fill the trenches completely with the p-type epitaxial layer and to form a p- and n-type columnar structure. The manufacturing process of the epitaxial trench filling method is shorter and simpler than the manufacturing process of the multi-step epitaxial growth method. Therefore, the epitaxial trench filling method facilitates reducing the manufacturing costs, with which a super-junction structure is manufactured.
However, when the p-type epitaxial layer is buried in the trenches by the epitaxial trench filling method, the p-type epitaxial layer will grow laterally on the mask oxide film in the final stage of filling the trench with the p-type epitaxial layer, if the mask oxide film is remaining on the wafer surface. The lateral growth of the p-type epitaxial layer (the additionally grown p-type epitaxial layer or the overgrown p-type epitaxial layer) impairs the crystallinity in the growth plane. If the time, for which the p-type epitaxial layer is additionally grown (overgrown), is long, crystal defects caused in the overgrown p-type epitaxial layer grown over the mask oxide will happen to diffuse sometimes to the semiconductor wafer below the mask oxide film. The crystal defects in the semiconductor wafer will remain, even if the overgrown p-type epitaxial layer is removed by surface polishing. The causes of leakage current increase are remaining in the semiconductor wafer, since the crystal defects are remaining in the semiconductor wafer.
It is therefore desirable to finish the epitaxial growth in the state, in which all the trenches are filled with respective silicon layers to the opening surface edges thereof by the epitaxial growth, without forming any overgrown epitaxial layer that causes the crystal defects as described above. However, growth rate variations are caused in every batch of epitaxial growth as well as in every wafer plane. Therefore, it is impossible in practice to finish the epitaxial growth in the state, in which all the trenches in the wafer are filled with the respective epitaxial growth layers without causing any under-growth or overgrowth. Since the expected device characteristics are not obtained when the trenches are not filled fully with the respective epitaxial layers due to epitaxial-growth-time shortage, the over epitaxial growth step described above is necessary and indispensable for the device manufacture.
For obviating the problems described above, it may be preferable to remove the mask oxide film that causes crystal defects prior to the step of fill the trenches with respective epitaxial growth layers. A method that facilitates removing the mask oxide film prior to filling the trenches with respective epitaxial growth layers has been disclosed. After removing the mask oxide film, the disclosed method fills the trenches with respective epitaxial growth layers employing an alignment marker disposed specially to form a super junction structure. See, for example, Japanese Unexamined Patent Application Publication No. 2005-317905.
A method for preventing voids from being caused and for easily flattening the wafer after the trenches are filled with respective epitaxial layers has been disclosed. The disclosed method laminates epitaxial films grown at a high growth rate. See, for example, Japanese Unexamined Patent Application Publication No. 2007-96137.
A method for manufacturing a super junction structure that fills trenches with an epitaxial film, having a flattened region in the surface thereof after a mask oxide film is removed and an alignment marker highly recognizable, has been disclosed. See, for example, Japanese Unexamined Patent Application Publication No. 2007-201499.
From the view point of manufacturing a device having a MOS structure, however, it is desirable for the mask oxide film to be remaining due to the reason described below. For forming a MOS structure in the surface portion of p- and n-type columns and for making the MOS structure work, it is necessary to position the MOS structure accurately on p- and n-type columns 2 and 7 as shown in FIG. 6. In order to position the MOS structure accurately on p- and n-type columns 2 and 7, it is necessary to position p-type base region 10 for each cell accurately as the cross sectional view of an SJ-MOS structure shown in FIG. 6 indicates. For accurately arranging p-type base region 10, it is desirable to form a marker, the image thereof is recognizable, in the oxide film prior to forming the p- and n-type columns and to accurately position a photomask on the silicon wafer using the marker in the patterning.
If a patterned oxide film is remaining after the trenches are filled with an epitaxial layer, the marker formed in the oxide film pattern can be recognized and utilized for positioning a photomask in the subsequent step. If the mask oxide film is removed completely and, then, trenches are filled with an epitaxial growth layer, a flat plane formed only of the epitaxial layer will be caused on the wafer surface. If the flat plane of the epitaxial layer is caused, the subsequent photo-step will not be conducted accurately, since any pattern that works for a mark does not exit.
When the mask oxide film is removed completely and silicon layers are buried in the respective trenches by epitaxial growth, it is necessary to overgrow the silicon layers after the silicon layers fill the trenches completely to prevent insufficient filling from causing in the wafer plane. Since the epitaxial growth rate varies from an epitaxial growth batch to an epitaxial growth batch, thickness variations will be caused among the overgrown epitaxial layers, even if the epitaxial growth is conducted for the same period. Since it is necessary to remove the p-type overgrown epitaxial layer by polishing after the growth thereof, it is necessary to measure the thickness of the overgrown epitaxial layer on every wafer in order to determine the polishing amount.
However, it is difficult to measure the overgrown epitaxial layer thickness non-destructively. Moreover, the non-destructive measurement on the overgrown epitaxial layer thickness is expensive. When the p-type overgrown epitaxial layer is polished deeply (in an over-polishing manner) assuming a certain thickness margin for the p-type overgrown epitaxial layer, variations will be caused among the depths of the buried p-type epitaxial layers after the polishing. An increase in a polishing amount increases variations of the polishing amount. The depth variations of the buried p-type epitaxial layers further cause large variations among the breakdown voltages of the devices. Therefore, it is difficult to remove the mask oxide film prior to the step of filling the trench with a silicon layer by the epitaxial growth method.
In view of the foregoing, it would be desirable to obviate the problems described above. It would be also desirable to provide a method for manufacturing a semiconductor device that facilitates preventing crystal defects due to a mask oxide film from being caused in manufacturing a super-junction semiconductor device by the epitaxial trench filling method, for further decreasing the leakage current and controlling the removal of an overgrown epitaxial layer on an SJ columnar structure, and for further confining the breakdown voltage distribution within a narrow range.